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| PRELIMINARY TECHNICAL DATA Preliminary Technical Data FEATURES 225 ps Propagation Delay through the Switch 4.5 Switch Connection between Ports Data Rate 1.244 Gbps 2.5 V/3.3 V Supply Operation Selectable Level Shifting/Translation Small Signal Bandwidth 610 MHz Level Translation 3.3 V to 2.5 V 3.3 V to 1.8 V 2.5 V to 1.8 V 24-Lead TSSOP and LFCSP Packages APPLICATIONS 3.3 V to 1.8 V Voltage Translation 3.3 V to 2.5 V Voltage Translation 2.5 V to 1.8 V Voltage Translation Bus Switching Bus Isolation Hot Swap Hot Plug Analog Signal Switching 2.5 V/3.3 V, 10-Bit, 2-Port Level Translating, Bus Switch ADG3246 FUNCTIONAL BLOCK DIAGRAM A0 B0 A9 B9 BE GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG3246 is a 2.5 V or 3.3 V, 10-bit, 2-port digital switch. It is designed on Analog Devices' low voltage CMOS process, which provides low power dissipation yet gives high switching speed and very low on resistance, allowing inputs to be connected to outputs without additional propagation delay or generating additional ground bounce noise. The switches are enabled by means of the Bus Enable (BE) input signal. These digital switches allow bidirectional signals to be switched when ON. In the OFF condition, signal levels up to the supplies are blocked. This device is ideal for applications requiring level translation. When operated from a 3.3 V supply, level translation from 3.3 V inputs to 2.5 V outputs occurs. Similarly, if the device is operated from a 2.5 V supply and 2.5 V inputs are applied, the device will translate the outputs to 1.8 V. In addition to this, the ADG3246 has a level translating select pin (SEL) . When SEL is low, VCC is reduced internally, allowing for level translation between 3.3 V inputs and 1.8 V outputs. This makes the device suited to applications requiring level translation between different supplies, such as converter to DSP/microcontroller interfacing. 1. 2. 3. 4. 5. 3.3 V or 2.5 V supply operation Extremely low propagation delay through switch 4.5 switches connect inputs to outputs Level/voltage translation 24-lead 4 mm x 4 mm LFCSP and 24-lead TSSOP packages REV. PrC Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved. ADG3246-SPECIFICATIONS1 Parameter DC ELECTRICAL CHARACTERISTICS Input High Voltage Input Low Voltage Input Leakage Current OFF State Leakage Current ON State Leakage Current Max Pass Voltage PRELIMINARY TECHNICAL DATA (VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.) B Version Typ2 Symbol VINH VINH VINL VINL II IOZ VP Conditions VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V 0 A, B VCC 0 A, B VCC VA/VB = VCC = SEL = 3.3 V, IO = -5 A VA/VB = VCC = SEL = 2.5 V, IO = -5 A VA/VB = VCC = 3.3 V, SEL = 0 V, IO = -5 A f = 1 MHz f = 1 MHz f = 1 MHz f = 1 MHz CL = 50 pF, VCC = SEL = 3 V VCC = 3.0 V to 3.6 V; SEL = VCC VCC = 3.0 V to 3.6 V; SEL = VCC VCC = 3.0 V to 3.6 V; SEL = 0 V VCC = 3.0 V tp 3.6 V; SEL = 0 V VCC = 2.3 V to 2.7 V; SEL = VCC VCC = 2.3 V to 2.7 V; SEL = VCC VCC = SEL = 3.3 V; VA/VB = 2 V VCC = SEL = 3.3 V; VA/VB = 2 V Min 2.0 1.7 Max Unit V V V V A A A V V V pF pF pF pF 2.0 1.5 1.5 0.01 0.01 0.01 2.5 1.8 1.8 5 5 10 6 0.8 0.7 1 1 1 2.9 2.1 2.1 CAPACITANCE3 A Port Off Capacitance B Port Off Capacitance A, B Port On Capacitance Control Input Capacitance SWITCHING CHARACTERISTICS3 Propagation Delay A to B or B to A, tPD4 Propagation Delay Matching5 Bus Enable Time BE to A or B6 Bus Disable Time BE to A or B6 Bus Enable Time BE to A or B6 Bus Disable Time BE to A or B6 Bus Enable Time BE to A or B6 Bus Disable Time BE to A or B6 Max Data Rate Channel Jitter Operating Frequency--Bus Enable DIGITAL SWITCH On Resistance CA OFF CB OFF CA, CB ON CIN tPHL, tPLH tPZH, tPZL tPHZ, tPLZ tPZH, tPZL tPHZ, tPLZ tPZH, tPZL tPHZ, tPLZ 1 1 0.5 0.5 0.5 0.5 3.2 3.2 2.2 1.7 2.2 1.75 1.244 50 0.225 22.5 4.8 4.8 3.3 2.9 3 2.6 fBE RON VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA VCC = 3 V, SEL = VCC, VA = 1.7 V, IBA = 8 mA VCC = 2.3 V, SEL = VCC, VA = 0 V, IBA = 8 mA VCC = 2.3 V, SEL = VCC, VA = 1 V, IBA = 8 mA VCC = 3 V, SEL = 0 V, VA = 0 V, IBA = 8 mA VCC = 3 V, SEL = 0 V, VA = 1 V, IBA = 8 mA VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA VCC = 3 V, SEL = VCC, VA = 1 V, IBA = 8 mA 2.3 ICC ICC ICC Digital Inputs = 0 V or VCC; SEL = VCC Digital Inputs = 0 V or VCC; SEL = 0 V VCC = 3.6 V, BE = 3.0 V; SEL = VCC 0.001 0.65 4.5 15 5 11 5 14 0.45 0.65 10 8 28 9 18 8 ns ps ns ns ns ns ns ns Gbps ps p-p MHz V A mA A On Resistance Matching POWER REQUIREMENTS VCC Quiescent Power Supply Current Increase in ICC per Input7 RON 3.6 1 1.2 130 NOTES 1 Temperature range is as follows: B Version: -40C to +85C. 2 Typical values are at 25C unless otherwise stated. 3 Guaranteed by design, not subject to production test. 4 The digital switch contributes no propagation delay other than the RC delay of the typical R ON of the switch and the load capacitance when driven by an ideal voltage source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 5 Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF. 6 See Timing Measurement Information. 7 This current applies to the control pin (BE) only. The A and B ports contribute no significant ac or dc currents as they transition. Specifications subject to change without notice. -2- REV. PrC PRELIMINARY TECHNICAL DATA ADG3246 ABSOLUTE MAXIMUM RATINGS* (TA = 25C, unless otherwise noted.) VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +4.6 V Digital Inputs to GND . . . . . . . . . . . . . . . . . -0.5 V to +4.6 V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . -0.5 V to +4.6 V DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150C LFCSP Package JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 35C/W TSSOP Package JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 128C/W Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300C IR Reflow, Peak Temperature (<20 seconds) . . . . . . . . 235C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. ORDERING GUIDE Model ADG3246BCP ADG3246BRU Temperature Range -40C to +85C -40C to +85C Package Description Chip Scale Package (LFCSP) Thin Shrink Small Outline Package (TSSOP) Package Option CP-24 RU-24 Table I. Pin Description Table II. Truth Table Pin Mnemonic BE SEL Ax Bx Description Bus Enable (Active Low) Level Translation Select Port A, Inputs or Outputs Port B, Inputs or Outputs BE L L H SEL* L H X Function A = B, 3.3 V to 1.8 V Level Shifting A = B, 3.3 V to 2.5 V/2.5V to 1.8 V Level Shifting Disconnect *SEL = 0 only when V DD = 3.3 V 10% PIN CONFIGURATION 24-Lead LFCSP and 24-Lead TSSOP 24 A4 23 A3 22 A2 21 A1 20 A0 19 V CC SEL 1 24 23 22 21 VCC BE B0 B1 B2 A0 2 18 BE 17 B0 16 B1 15 B2 14 B3 13 B4 SEL 1 A5 2 A6 3 A7 4 A8 5 A9 6 PIN 1 INDICATOR A1 3 A2 4 A3 5 A4 6 ADG3246 TOP VIEW ADG3246 20 TOP VIEW 19 B3 A5 7 (Not to Scale) 18 B4 17 16 15 14 13 GND 7 B9 8 B8 9 B7 10 B6 11 B5 12 A6 8 A7 9 A8 10 A9 11 GND 12 B5 B6 B7 B8 B9 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG3246 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. PrC -3- PRELIMINARY TECHNICAL DATA ADG3246 TERMINOLOGY VCC GND VINH VINL II IOZ IOL VP RON RON CX OFF CX ON CIN ICC ICC tPLH, tPHL tPZH, tPZL tPHZ, tPLZ Positive Power Supply Voltage Ground (0 V) Reference Minimum Input Voltage for Logic 1 Maximum Input Voltage for Logic 0 Input Leakage Current at the Control Inputs OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state. ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state. Max Pass Voltage. The max pass voltage relates to the clipped output voltage of an NMOS device when the switch input voltage is equal to the supply voltage. Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified amount of current through the switch. On Resistance Match between Any Two Channels, i.e., RON Max - RON Min OFF Switch Capacitance ON Switch Capacitance Control Input Capacitance. This consists of BE and SEL. Quiescent Power Supply Current. It is measured when all control inputs are at a logic HIGH or LOW level and the switches are OFF. Extra Power Supply Current Component for the BE Control Input when the Input is not Driven at the Supplies Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant RON x CL, where CL is the load capacitance. Bus Enable Times. These are times taken to cross the VT voltage at the switch output when the switch turns on in response to the control signal, BE. Bus Disable Times. This is the time taken to place the switch in the high impedance OFF state in response to the control signal. It is measured as the time taken for the output voltage to change by V from the original quiescent level, with reference to the logic level transition at the control input. (Refer to Figure 3 for enable and disable times.) Maximum Rate at which Data Can Be Passed through the Switch Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel Operating Frequency of Bus Enable. This is the maximum frequency at which Bus Enable (BE) can be toggled. Max Data Rate Channel Jitter fBEx -4- REV. PrC PRELIMINARY TECHNICAL DATA Typical Performance Characteristics-ADG3246 40 35 30 25 TA = 25 C SEL = VCC VCC = 3V 40 35 30 25 TA = 25 C SEL = VCC VCC = 2.3V 40 35 30 25 VCC = 2.5V 20 15 VCC = 2.7V 10 5 0 VCC = 3.6V 10 5 0 0.5 1.0 2.0 1.5 VA/VB - V 2.5 3.0 3.5 0 0 0.5 1.0 2.0 1.5 VA/VB - V 2.5 3.0 10 5 0 TA = 25 C SEL = 0V VCC = 3V RON - RON - VCC = 3.3V 20 15 RON - VCC = 3.3V 20 15 VCC = 3.6V 0 0.5 1.0 1.5 2.0 VA/VB - V 2.5 3.0 3.5 TPC 1. On Resistance vs. Input Voltage TPC 2. On Resistance vs. Input Voltage TPC 3. On Resistance vs. Input Voltage 20 VCC = 3.3V SEL = VCC 15 15 VCC = 2.5V SEL = VCC 3.0 2.5 TA = 25 C SEL = VCC IO = -5 A VCC = 3.6V RON - 85 C VOUT - V 10 2.0 1.5 VCC = 3.3V VCC = 3V RON - 10 85 C 5 5 1.0 40 C 25 C 25 C 40 C 0.5 0 0 0.5 1.0 VA/VB - V 1.5 2.0 0 0 0 0.5 VA/VB - V 1.0 1.2 0 0.5 1.0 2.0 1.5 VCC - V 2.5 3.0 3.5 TPC 4. On Resistance vs. Input Voltage for Different Temperatures TPC 5. On Resistance vs. Input Voltage for Different Temperatures TPC 6. Pass Voltage vs. VCC 2.5 TA = 25 C SEL = VCC IO = -5 A VCC = 2.7V 2.5 TA = 25 C SEL = 0V IO = -5 A VCC = 3.6V 1800 1600 1400 1200 VCC = 3.3V, SEL = 0V TA = 25 C 2.0 2.0 VOUT - V VCC = 2.5V VCC = 2.3V VCC = 3.3V 1.0 VCC = 3V ICC - A 1.5 VOUT - V 1.5 1000 800 600 1.0 0.5 0.5 400 200 VCC = SEL = 3.3V VCC = SEL = 2.5V 0 2 4 6 8 10 12 14 16 18 20 ENABLE FREQUENCY - MHz 0 0 0.5 1.0 1.5 2.0 VCC - V 2.5 3.0 0 0 0.5 1.0 1.5 2.0 VCC - V 2.5 3.0 3.5 0 TPC 7. Pass Voltage vs. VCC TPC 8. Pass Voltage vs. VCC TPC 9. ICC vs. Enable Frequency REV. PrC -5- PRELIMINARY TECHNICAL DATA ADG3246 3.0 2.5 TA = 25 C VA = 0V BE = 0 VCC = 3.3V; SEL = 0V VOUT - V 3.0 2.5 TA = 25 C VA = VCC BE = 0 VCC = SEL = 3.3V QINJ - pC 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 VCC = 3.3V VCC = 2.5V TA = 25 C SEL = VCC ON OFF CL = InF 2.0 VOUT - V 2.0 1.5 VCC = SEL = 3.3V 1.5 1.0 1.0 V = SEL = 2.5V CC 0.5 VCC = SEL = 2.5V 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 IO - A VCC = 3.3V; SEL = 0V 0 -0.10 -0.09 -0.08 -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 IO - A 0.5 0 -1.8 -2.0 0 0.5 1.0 1.5 2.0 VA/VB - V 2.5 3.0 TPC 10. Output Low Characteristic TPC 11. Output High Characteristic TPC 12. Charge Injection vs. Source Voltage 0 -2 TA = 25 C VCC = 3.3V/2.5V SEL = V CC VIN = 0dBm N/W ANALYZER: RL = RS = 50 -20 -30 ATTENUATION - dB -40 -50 -60 -70 -80 -90 -100 0.03 0.1 1 10 100 FREQUENCY - MHz 1000 0.03 0.1 1 10 100 FREQUENCY - MHz 1000 TA = 25 C VCC = 3.3V/2.5V SEL = V CC ADJACENT CHANNELS VIN = 0dBm N/W ANALYZER: RL = RS = 50 -20 -30 ATTENUATION - dB ATTENUATION - dB -40 -50 -60 -70 -80 -90 -4 -6 -8 TA = 25 C VCC = 3.3V/2.5V SEL = V CC VIN = 0dBm N/W ANALYZER: RL = RS = 50 -10 -12 -14 -100 0.03 0.1 1 10 100 FREQUENCY - MHz 1000 TPC 13. Bandwidth vs. Frequency TPC 14. Crosstalk vs. Frequency TPC 15. Off Isolation vs. Frequency 3.5 ENABLE 3.0 DISABLE 2.5 TIME - ns ENABLE TIME - ns 2.0 DISABLE 1.5 1.0 VCC = 3.3V, SEL = 0V VCC = SEL = 3.3V 2.5 100 90 VCC = SEL = 3.3V VIN = 2V p-p 20dB ATTENUATION 2.0 ENABLE VCC = SEL = 2.5V JITTER - ps 0 20 40 60 TEMPERATURE - C 80 100 DISABLE 80 70 60 50 40 30 1.5 1.0 0.5 20 10 0.5 0 -40 0 -40 -20 0 20 40 60 TEMPERATURE - C 80 100 -20 0 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 DATA RATE - GBPS TPC 16. Enable/Disable Time vs. Temperature TPC 17. Enable/Disable Time vs. Temperature TPC 18. Jitter vs. Data Rate; PRBS 31 -6- REV. PrC PRELIMINARY TECHNICAL DATA ADG3246 100 95 90 VCC = SEL = 3.3V VIN = 2V p-p 20dB ATTENUATION EYE WIDTH - % 85 80 75 70 65 60 55 35mV/DIV 100ps/DIV % EYE WIDTH = ((CLOCK PERIOD - JITTER p-p)/CLOCK PERIOD) 100% VCC = 3.3V SEL = 3.3V VIN = 2V p-p 20dB ATTENUATION TA = 25 C 37mV/DIV 200ps/DIV VCC = 2.5V SEL = 2.5V VIN = 2V p-p 20dB ATTENUATION TA = 28 C 50 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 DATA RATE - GBPS TPC 19. Eye Width vs. Data Rate; PRBS 31 TPC 20. Eye Pattern; 1.244 GBPS, VCC = 3.3 V, PRBS 31 TPC 21. Eye Pattern; 1 GBPS, VCC = 2.5 V, PRBS 31 50.1mV/DIV 50ps/DIV TA = 25 C 20dB ATTENUATION VCC = 3.3V SEL = 3.3V VIN = 2V p-p TPC 22. Jitter @ 1.244 GBPS, PRBS 31 REV. PrC -7- PRELIMINARY TECHNICAL DATA ADG3246 TIMING MEASUREMENT INFORMATION For the following load circuit and waveforms, the notation that is used is VIN and VOUT where: VIN = VA and VOUT = VB or VIN = VB and VOUT = VA VCC SW1 VIH 2 VCC CONTROL INPUT BE VT VIN PULSE GENERATOR RT D.U.T. VOUT RL GND tPLH VOUT tPHL 0V VH VT VL CL RL Figure 2. Propagation Delay NOTES PULSE GENERATOR FOR ALL PULSES: tR 2.5ns, tF 2.5ns, FREQUENCY 10MHz CL INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES . RT IS THE TERMINATION RESISTOR, SHOULD BE EQUAL TO ZOUT OF THE PULSE GENERATOR. Figure 1. Load Circuit Test Conditions Symbol RL V CL VT VCC = 3.3 V 0.3 V (SEL = VCC) 500 300 50 1.5 VCC = 2.5 V 0.2 V (SEL = VCC) 500 150 30 0.9 VCC = 3.3 V 0.3 V (SEL = 0 V) 500 150 30 0.9 Unit mV pF V ENABLE CONTROL INPUT BE DISABLE VINH VT 0V tPZL VOUT SW1 @ 2VCC VCC VT tPLZ VCC VL + V VL Table III. Switch Position VIN = 0V TEST tPLZ, tPZL tPHZ, tPZH S1 2 x VCC GND tPZH VIN = VCC VOUT SW1 @ GND VT 0V tPHZ VH VH - V 0V Figure 3. Enable and Disable Times -8- REV. PrC PRELIMINARY TECHNICAL DATA ADG3246 BUS SWITCH APPLICATIONS Mixed Voltage Operation, Level Translation 2.5 V to 1.8 V Translation Bus switches can be used to provide an ideal solution for interfacing between mixed voltage systems. The ADG3246 is suitable for applications where voltage translation from 3.3 V technology to a lower voltage technology is needed. This device can translate from 3.3 V to 1.8 V, from 2.5 V to 1.8 V, or bidirectionally from 3.3 V directly to 2.5 V. Figure 4 shows a block diagram of a typical application in which a user needs to interface between a 3.3 V ADC and a 2.5 V microprocessor. The microprocessor may not have 3.3 V tolerant inputs, therefore placing the ADG3246 between the two devices allows the devices to communicate easily. The bus switch directly connects the two blocks, thus introducing minimal propagation delay, timing skew, or noise. 3.3V When VCC is 2.5 V (SEL = VCC) and the input signal range is 0 V to VCC, the max output signal will, as before, be clamped to within a voltage threshold below the VCC supply. 2.5V 2.5V ADG3246 1.8V Figure 7. 2.5 V to 1.8 V Voltage Translation, SEL = VCC 3.3V 2.5V In this case, the output will be limited to approximately 1.8 V, as shown in Figure 7. VOUT 2.5V SUPPLY SEL = 2.5V ADG3246 3.3V ADC 2.5V MICROPROCESSOR 1.8V SWITCH OUTPUT Figure 4. Level Translation between a 3.3 V ADC and a 2.5 V Microprocessor 3.3 V to 2.5 V Translation 0V When VCC is 3.3 V (SEL = VCC) and the input signal range is 0 V to VCC, the max output signal will be clamped to within a voltage threshold below the VCC supply. 3.3V SWITCH INPUT VIN 2.5V Figure 8. 2.5 V to 1.8 V Voltage Translation, SEL = VCC 3.3 V to 1.8 V Translation The ADG3246 offers the option of interfacing between a 3.3 V device and a 1.8 V device. This is possible through use of the SEL pin. 2.5V 3.3V ADG3246 2.5V 2.5V SEL pin: An active low control pin. SEL activates internal circuitry in the ADG3246 that allows voltage translation between 3.3 V devices and 1.8 V devices. 3.3V Figure 5. 3.3 V to 2.5 V Voltage Translation, SEL = VCC In this case, the output will be limited to 2.5 V, as shown in Figure 6. VOUT 2.5V SWITCH OUTPUT 3.3V ADG3246 1.8V 3.3V SUPPLY SEL = 3.3V Figure 9. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V 0V SWITCH INPUT VIN 3.3V When VCC is 3.3 V and the input signal range is 0 V to VCC, the max output signal will be clamped to 1.8 V, as shown in Figure 9. To do this, the SEL pin must be tied to Logic 0. If SEL is unused, it should be tied directly to VCC. Figure 6. 3.3 V to 2.5 V Voltage Translation, SEL = VCC This device can be used for translation from 2.5 V to 3.3 V devices, and also between two 3.3 V devices. REV. PrC -9- PRELIMINARY TECHNICAL DATA ADG3246 ADG3246 ADG3246 VOUT 1.8V CPU SWITCH OUTPUT 3.3V SUPPLY SEL = 0V PLUG-IN CARD (1) CARD I/O RAM 0V SWITCH INPUT VIN 3.3V PLUG-IN CARD (2) CARD I/O Figure 10. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V Bus Isolation A common requirement of bus architectures is low capacitance loading of the bus. Such systems require bus bridge devices that extend the number of loads on the bus without exceeding the specifications. Because the ADG3246 is designed specifically for applications that do not need drive yet require simple logic functions, it solves this requirement. The device isolates access to the bus, thus minimizing capacitance loading. Load A Load C Figure 12. ADG3246 in a Hot Plug Application There are many systems that require the ability to handle hot swapping, such as docking stations, PCI boards for servers, and line cards for telecommunications switches. If the bus can be isolated prior to insertion or removal, then there is more control over the hot swap event. This isolation can be achieved using a bus switch. The bus switches are positioned on the hot swap card between the connector and the devices. During hot swap, the ground pin of the hot swap card must connect to the ground pin of the back plane before any other signal or power pins. Analog Switching Bus/ Backplane Load B Load D Bus Switch Location Figure 11. Location of Bus Switched in a Bus Isolation Application Hot Plug and Hot Swap Isolation Bus switches can be used in many analog switching applications; for example, video graphics. Bus switches can have lower on resistance, smaller ON and OFF channel capacitance and thus improved frequency performance than their analog counterparts. The bus switch channel itself consisting solely of an NMOS switch limits the operating voltage (see TPC 1 for a typical plot), but in many cases this does not present an issue. High Impedance During Power-Up/Power-Down The ADG3246 is suitable for hot swap and hot plug applications. The output signal of the ADG3246 is limited to a voltage that is below the VCC supply, as shown in Figures 6, 8, and 10. Therefore the switch acts like a buffer to take the impact from hot insertion, protecting vital and expensive chipsets from damage. In hot-plug applications, the system cannot be shutdown when new hardware is being added. To overcome this, a bus switch can be positioned on the backplane between the bus devices and the hot plug connectors. The bus switch is turned off during hot plug. Figure 12 shows a typical example of this type of application. To ensure the high impedance state during power-up or powerdown, BE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the currentsinking capability of the driver. PACKAGE AND PINOUT The ADG3246 is packaged in both a small 24-lead TSSOP or a tiny 24-lead LFCSP package. The area of the TSSOP option is 49.375 mm2, while the area of the LFCSP option is 16 mm2. This leads to a 67% savings in board space when using the LFCSP package compared with the TSSOP package. This makes the LFCSP option an excellent choice for space-constrained applications. The ADG3246 in the TSSOP package offers a flowthrough pinout. The term flowthrough signifies that all the inputs are on opposite sides from the outputs. A flowthrough pinout simplifies the PCB layout. -10- REV. PrC PRELIMINARY TECHNICAL DATA ADG3246 OUTLINE DIMENSIONS 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 4 mm Body (CP-24) Dimensions shown in millimeters 4.0 BSC SQ 0.60 MAX 0.60 MAX 19 18 24 1 0.25 MIN PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 3.75 BSC SQ 0.50 BSC 0.50 0.40 0.30 BOTTOM VIEW 13 12 7 6 2.25 1.70 SQ 0.75 1.00 0.90 0.85 0.25 REF 12 MAX 1.00 MAX 0.65 NOM 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 2.50 REF SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 0.10 COPLANARITY 1.20 MAX SEATING PLANE 0.20 0.09 8 0 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AD REV. PrC -11- -12- C03012-0-2/03(PrC) PRINTED IN U.S.A. |
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